1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly, to a bond pad of a semiconductor device formed by a damascene technique using copper and a method of fabricating the same.
2. Description of the Related Art
As the integration density of semiconductor devices increases, in the case of a logic semiconductor device requiring high integration and high operating speed, the thickness of a gate oxide layer and the size of a gate have been reduced to improve the operating speed. However, it is further effective to improve the operating speed of the logic semiconductor device by reducing the resistance of a line connected to the logic semiconductor device and the parasitic capacitance of an inter-metal dielectric layer.
To meet such a requirement, a copper pattern using a damascene technique has been applied. Generally, copper has a resistivity of 1.59 [xcexc xcexa9xc2x7cm] while aluminum used as the existing line material has a resistivity of 2.66 [xcexc xcexa9xc2x7cm]. The resistivity of copper is 60% lower than that of aluminum. Also, the cost of copper is lower than that of aluminum and the electro-migration life thereof is relatively long. Electro-migration is a phenomenon in which the metal line formed in a semiconductor device moves from one region to another or is bent due to heat and high current density. Consequently, copper is being considered as a next generation line material.
However, it is difficult to apply photolithographic and etch processes to a copper pattern. Therefore, when a copper pattern is applied to a semiconductor device, photolithographic and etch processes are not used. Instead, copper is filled into a dielectric layer by the damascene technique and polished by a chemical mechanical polishing process, thereby forming a copper pattern.
FIGS. 1 and 2 show cross-sectional and plane views, respectively, of a bond pad of a semiconductor device according to the prior art. Referring to FIGS. 1 and 2, multilayered copper patterns 20, 30, and 40 are formed on a semiconductor substrate 10. The multilayered copper patterns 20, 30 and 40 are electrically connected to one another through a plurality of plugs 26 and 36 formed at diffusion barrier layers 22 and 32 and inter-metal dielectric layers 24 and 34. The copper pattern 40, which is exposed at the top of the structure, is used as a bond pad 60, and a passivation layer 50 is formed on the copper pattern 40 to protect the semiconductor chip from external environmental effects.
If a broad metal line region such as the bond pad 60 is polished by chemical mechanical polishing, it is polished faster than other narrow metal line regions. As a result, dishing D occurs. Dishing is a structural phenomenon in which a broad metal line region is highly polished during a chemical mechanical polishing process, in which the broad metal line region is dented and a step difference is generated.
Such a step difference causes damage to peripheral circuits during the chemical mechanical polishing process. Also, in a case where a multilayered metal line is formed by continuous chemical mechanical polishing, the dishing generated in a broad metal line region such as the bond pad 60 is accumulated toward the upper layers. Consequently, it may cause serious problems to the planarization in the chemical mechanical polishing process.
To solve the above problems, it is an object of the present invention to provide a bond pad of a semiconductor device having means for restraining dishing generated in a chemical mechanical polishing process by dividing a copper pattern serving as a bond pad into several copper patterns and effectively preventing an increase in line resistance which would otherwise be caused by dividing the copper pattern.
It is another object of the present invention to provide a method of fabricating a bond pad of a semiconductor device.
Accordingly, to achieve the above first object, there is provided a bond pad structure of a semiconductor device. The bond pad structure includes a semiconductor substrate including a lower dielectric layer and a lower copper pattern, a first dielectric layer pattern formed in the semiconductor substrate with a contact hole connected to the lower copper pattern. A first copper pattern is filled into the first dielectric layer pattern by a damascene technique to be connected to the lower copper pattern. A second dielectric layer pattern of a second form different from the first dielectric layer pattern is formed on the first copper pattern and has a contact hole connected to the first copper pattern and a line connection structure horizontally connecting separated parts to one another. A second copper pattern is filled into the second dielectric layer pattern by a damascene technique to be connected to the first copper pattern. A passivation layer is formed on the second copper pattern, and a bond pad is formed by patterning a portion of the passivation layer. A conductivity improving layer is formed on the exposed second copper pattern of the bond pad.
In one embodiment, first, second, and third diffusion barrier layers made of nitride are formed on the lower copper pattern, the first copper pattern, and the second copper pattern, respectively.
The first and second dielectric layer patterns have structures in which the first and second copper patterns filled into the first and second dielectric layers are connected to each other in the vertical direction or the horizontal direction without separation.
The conductivity improving layer is formed of a material selected from the group consisting of Ta, TaN, Al, Ti, TiN, TaSiN, Au, W and Nb on the first and second copper patterns. Thus, the line resistance which would otherwise have increased when the first and second copper patterns having lattice models are made can be effectively reduced.
In accordance with the invention, there is also provided a method of fabricating a bond pad of a semiconductor device. A semiconductor substrate including a lower dielectric layer and a lower copper pattern is prepared. A first dielectric layer pattern is formed by stacking and patterning a first diffusion barrier layer on the semiconductor substrate and forming a dual damascene line. A first copper pattern is formed to fill the first dielectric layer by stacking a copper layer on the semiconductor substrate on which the first dielectric layer pattern is formed and performing a chemical mechanical polishing process. A second dielectric layer pattern is formed by stacking a second diffusion barrier layer on the semiconductor substrate on which the first copper pattern is formed and forming a dual damascene line. A second copper pattern is formed to fill the second dielectric layer by stacking a copper layer on the semiconductor substrate on which the second dielectric layer pattern is formed and performing a chemical mechanical polishing process. A conductivity improving layer is formed on a region in which a bond pad will be formed on the semiconductor substrate on which the second copper pattern is formed. The bond pad is formed to expose the conductivity improving layer pattern by forming and patterning a passivation layer on the semiconductor substrate on which the conductivity improving layer pattern is formed.
In accordance with the invention, another method of fabricating a bond pad of a semiconductor device is provided. A semiconductor substrate including a lower dielectric layer and a lower copper pattern is prepared. A first dielectric layer pattern is formed by stacking a first diffusion barrier layer on the semiconductor substrate and forming a dual damascene line. A first copper pattern is formed to fill the first dielectric layer by stacking a copper layer on the semiconductor substrate on which the first dielectric layer pattern is formed and performing a chemical mechanical polishing process. A second dielectric layer pattern is formed by stacking a second diffusion barrier layer on the semiconductor substrate on which the first copper pattern is formed and forming a dual damascene line. A second copper pattern is formed to fill the second dielectric layer by stacking a copper layer on the semiconductor substrate on which the second dielectric layer pattern is formed and performing a chemical mechanical polishing process. The second copper pattern on which a bond pad will be formed is opened by stacking and patterning a passivation layer. A conductivity improving layer is deposited on the semiconductor substrate and then is polished by chemical mechanical polishing. As a result, the conductivity improving layer is formed only in the bond pad.
The first and second dielectric layer patterns can have line connection structures horizontally connecting the separated first and second copper patterns filled into the first and second dielectric layer patterns.
In the method of forming the first and second copper patterns, a barrier layer can be formed on the first and second dielectric layer patterns, a copper seed layer is formed on the barrier layer and the seed layer is grown by an electroplating method.
The first and second dielectric layer patterns electrically connect the entire separated first and second copper patterns filled into the first and second dielectric layer patterns in the vertical direction. Preferably, a conductivity improving layer may be further formed on the first copper pattern.
According to the present invention, dishing, which occurs in a chemical mechanical polishing process, can be prevented by forming first and second copper patterns having lattice structures. Also, a line resistance is increased when the first and second copper patterns having lattice structures are formed. The line resistance can be reduced by first and second dielectric layers which connect the first and second copper patterns in the vertical or horizontal direction. In addition, the line resistance can be reduced by a line connection structure which connects the separated first and second copper patterns, horizontally, which are formed on the first and second dielectric layer patterns. Also, the line resistance can be reduced by a conductivity improving layer which is formed on the first and second copper patterns.